In recent years, research and development are conducted on a nonvolatile memory device having memory cells that use variable resistance elements. A variable resistance element is an element that has a property that a resistance value changes (the variable resistance element changes between a high resistance state and a low resistance state) according to an electrical signal and enables information to be written through this change in resistance value.
One structure of memory cells using variable resistance elements is a cross point structure. In the cross point structure, each memory cell is placed at a different one of cross points of orthogonally arranged bit lines and word lines so as to be provided between a bit line and a word line. Various types of such cross point variable resistance nonvolatile memory devices are developed in recent years (for example, see Patent Literatures (PTLs) 1 and 2).
PTL 1 discloses a nonvolatile memory device having memory cells that use bidirectional variable resistors in the cross point structure. More specifically, PTL 1 discloses that a varistor, for instance, is used as a bidirectional nonlinear element included in each memory cell, in order to reduce a leakage current which flows into an unselected memory cell, and that reading is performed by applying, at the time of reading, a read voltage Vr to a selected bit line, VSS to a selected word line, and a voltage lower than the read voltage Vr to an unselected word line and an unselected bit line.
PTL 2 also discloses a nonvolatile memory device having a cross point memory cell array in which each memory cell including a bidirectional variable resistor and a bidirectional nonlinear element is placed at a different one of cross points of word lines arranged in parallel with each other and bit lines arranged orthogonal to the word lines, so as to form a matrix. PTL 2 discloses that the bidirectional nonlinear element is designed to reduce a leakage current that flows through unselected memory cells. Since, however, an amount of leakage current depends on an array size of a memory cell array, an increase in array size causes a significant increase in leakage current. In response to such a problem, PTL 2 discloses, as a method of reducing a leakage current, a means for applying a predetermined voltage to an unselected word line and an unselected bit line, thereby enabling more stable reading.